OZARK INTEGRATED CIRCUITS INC — National Aeronautics and Space Administration SBIR Phase I: S13

Description

NASA has demonstrated a resolve to land instruments on the corrosive, high-pressure (~100 bar), high-temperature (470deg;C) surface of Venus. NASA Glenn Research Centerrsquo;s JFET-R technology is the only one that has shown 1000rsquo;s of hours operation under Venus surface conditions. NASA desires computational analyses on the surface of Venus. Ozark IC is currently working on a NASA Phase II to create an all-SiC based RISC-V microprocessor in parallel with a rugged high-density packaging system. For this computational system to achieve maximum potential, access to a high temperature read only memory is critical. Companies like Cerfenbsp; and UPennnbsp;are creating high temperature thin film non-volatile memory (NVM) technologies. In this project, Ozark IC will utilize its extensive experience in rugged additive manufacturing to create a macro scale thick-film HT ROM technology as an alternative technology.This proposalrsquo;s objective is an all-additive ROM that will integrate well with the JFET-R technology or accompany, off chip, a microprocessor module.The project will design, simulate, package, and characterize an all-additive ROM technology based on materials that were qualified up to TRL-5 in previous NASA SBIR programs. This work will first attempt to create an all-additive ROM structure in which each bit is created, or ldquo;programmedrdquo; during manufacturing. Ozark IC will also investigate using this technology for programming the ROM once, after manufacturing. Each design will be tested at 500deg;C to validate feasibility of Venus surface operation. Parallel work will investigate SiC thin film options for ROMs as well as all the necessary read-out electronics using JFET-R for any of these ROM structures. The body of this work will culminate in a scalable ROM structure that can accompany the SiC RISC-V chipset in a single heterogenous package.Ozark IC is well positioned to determine and address the requirements of these ROM memory structures from its work on the RISC-V microprocessor.