PACIFIC MICROCHIP CORP. — Department of Energy SBIR Phase I: C53-33b

Description

NP detectors are undergoing a paradigm shift towards streaming readout technologies to replace the triggered readout. These detectors employ thousands of readout channels working at increasingly high event rate. If based on of-the-shelf components, the electronics occupy large volume, dissipate excessive heat and cannot tolerate high TID levels. Pacific Microchip Corp. proposes to develop a TID tolerant ASIC to support high-speed streaming readout for multichannel detectors. The ASIC includes a continuously sampling 32-channel 12-bit 1GS/s ADC IP block and a high-performance DSP block with an event building back-end. The ADC will digitize while the DSP block will shape the event related pulses, restore the baseline, detect the pulse peak, analyze its amplitude, timing, add the channel address information, compress the data and ship it out. This ASIC will facilitate the detector systems to support streaming readout while increasing the readout speed, TID tolerance, cost effectiveness, robustness and will lower power consumption. In Phase I, the ASIC’s architecture will be developed, the TID immunity of the ADC IP block will be tested, the critical circuits will be designed, and the proof of feasibility will be provided. Phase II will result in the fabricated and tested ASIC’s prototype. Examples of commercial applications for the proposed ASIC include radiography instruments in medicine, imaging systems for airport security, border/customs control, industrial radiography systems for non-destructive defect detection. Currently, there is no TID tolerant ASIC that can perform the DSP function simultaneously in 32 channels on event produced pulses digitized at 1GS/s. The ASIC will be provided as a component, and as an IP block. According to “Research and Markets”, the global smart sensor technology market is growing annually at a CAGR of 10.4% and is expected to reach $242B by 2025. This projection confirms the great commercial potential for the proposed ASIC.