ALPHACORE INC — National Aeronautics and Space Administration SBIR Phase I: S11

Description

Alphacore will develop a low cost, radiation-hardened Scalable Data Acquisition System (SDAS) based on an innovative application-specific integrated circuit (ASIC) for Microwave Kinetic Inductance Detectors (MKIDs). The proposed SDAS ASIC will have 4-8 channels for 14-bit accurate Analog to Digital Conversion (ADC) and Digital to Analog Conversion (DAC, for carrier tone generation) with each channel handling gt;4GHz of bandwidth (instantaneous bandwidth of gt; 8GHz at 4GS/s per ASIC and tunable bandwidth range of 16GHz) while consuming less than 40 mW per detector readout chain. The SDAS will also have a low power I/O (input/output) user interface with a programmable LVDS. The SDAS ASIC will have several programmable operation modes, with bandwidths of operation of more than 4GHz. In addition, the SDAS will also include flexible intermediate frequency (IF) electronics with a loopback mode for IQ autocalibration and dynamic range measurements. The combination of the digital signal processing and integrated I/O and flexible IF electronics will enable it to serve many millimeter to sub-millimeter-wave experiments.Alphacorersquo;s proposed ultra-low power, rad-hard SDAS system will provide exceptional value to NASA by delivering a combination of performance, robustness, and flexibility with the minimum size, weight and power (SWaP). Alphacorersquo;s SDAS will include a high-performance DDS (Direct Digital Synthesizer), an integral part of any KID array readout system needed to provide the gigahertz stimulus to the detectors. Alphacorersquo;s key innovations include 1) silicon proven innovative calibration methodologies for ADCs operating in harsh (radiation) environments, 2) small area, ultra-low power polyphase filter bank using re-quantization technique, nbsp;3) Low power programmable-eye-LVDS based SERDES, and 4) silicon proven ultra-low power all-digital DDS.nbsp; Alphacorersquo;s existing circuit blocks can be leveraged in this work to mitigate risk in designing a complex high-performance ASIC.