PACIFIC MICROCHIP CORP. — National Aeronautics and Space Administration SBIR Phase I: H9
PACIFIC MICROCHIP CORP. — SBIR Phase I award from National Aeronautics and Space Administration.
Phase I SBIR feasibility signal
- Phase I awards fund proof-of-concept work. For capture teams, they mark early interest from National Aeronautics and Space Administration in a technical approach.
- Watch for Phase II follow-ons from the same firm/topic family — that conversion path is where budgets and transition pressure rise.
- Obligated amount $131,499. Cross-check similar awards in the same agency and technology tags for going-rate context.
- Topic code H9 links this award to a solicitation family — search the same topic stem for incumbents and recompete timing.
- Amount
- $131,499
- Agency
- National Aeronautics and Space Administration
- Program / Phase
- SBIR · Phase I
- Topic
- H9
- Solicitation
- SBIR_21_P1
- NAICS
- —
- Place of performance
- CA
- Period
- 2021-05-03 → 2021-11-19
Description
Pacific Microchip Corp. proposes to develop an ADC implementing fundamentally new architecture employing a single stage voltage-to-charge-to-digital converter based on a charge ramping quantizer (CRQ). The CRQ removes traditional barriers such as large number of comparators (Flash architecture), slow binary search (SAR architecture), power hungry and slow continuous-time comparators and large silicon area consuming time-to-digital converters (temporal ADC). By removing these barriers and taking full benefit of modern CMOS processes, the CRQ offers a high sampling rate at greatly reduced power consumption. A single sub-ADC based on this architecture demonstrates over 4 times speed improvement compared to a SAR ADC. The project will target 8-bit resolution and 56GS/s rate. Instead of overdesigning, when seeking to maximize the performance, the ADC will rely on parameter calibration using a built-in CPU. On-chip phase locked loops (PLLs) will be used for clock synthesis. For convenient interfacing with field programmable gate arrays (FPGAs) at up to 64x8.8Gb/s, the ADC will include a JESD204B standard compliant interface. Phase I work will provide the proof of ADC feasibility ndash; critical blocks will be implemented and verified at the targeted technology node. At Phase II, a silicon proven prototype ADC will be provided.