ATC-NY INC — Department of Defense SBIR Phase II: DTRA172-003

Description

Next-generation high-performance computing (HPC) hardware, such as the Intel Xeon Phi Knights Landing Many-Integrated-Core processor, provide new deep memory architectures that offer the promise of increased performance. The challenge in taking full advantage of this architecture is selecting which data structures will be placed in the high-bandwidth memory. Optimizing data structure placement in memory is a task that requires the assistance of automated tools. To address this need, ATC-NY is developing the Memory Instrumentation and Performance Simulation (MIPS) software, a memory analysis and optimization tool aimed at next-generation HPC memory architectures. MIPS directly instruments as-built optimized binaries (without requiring source code or modification of the software build process) models the behavior of the complete memory hierarchy of a system, and uses this analysis to produce intelligent, actionable advice on memory placement. MIPS also provides the cutting-edge capability to apply memory placement optimization without requiring source code changes, enabling a single software executable to be used on differently-configured systems and for different use cases without requiring software re-engineering and without giving up any potential performance.