BROWN DEER TECHNOLOGY LLC — Department of Defense SBIR Phase I: A20-003

Description

The DARPA-funded RISC-V architecture reflects a potentially disruptive shift towards open-hardware design and standardization in a computer industry that has been dominated by closed proprietary instruction set architectures (ISAs) for decades.  The modular and extensible design of RISC-V enables a foundation for generally-specialized architectures for greater power-performance efficiency as we witness an end to Dennard Scaling and Moore's Law.  The potential for a RISC-V based Digital Signal Processor (DSP) is significant and would address many critical challenges in the deployment of signal processing applications.  The engineered extensibility in the RISC-V ISA provides additional support for exploring a RISC-V DSP with both standards-based extensions and proprietary application-specific customization.  We propose to develop a family of customizable RISC-V DSP architectures targeting different application deployments ranging from ultra-low-power embedded to more high-performance general-purpose processors with DSP specialization.  Using a common foundation of interoperable DSP ISA extensions, special attention will be given to the more challenging constraints of embedded edge-device applications with strict power and space constraints.  Each DSP processor will implement the base RISC-V ISA along with complementary standard extensions appropriate for the target application space.  A modular DSP extension to the RISC‑V ISA will be developed to include extensions for complex floating-point arithmetic, real and complex fixed-point arithmetic, and streaming instructions.  All processors will enforce a strict true Harvard architecture memory model that goes even further to include separable memory segments for application performance.  Enforcing a true Harvard architecture for DSP applications has important implications for performance security.