INDIANA INTEGRATED CIRCUITS LLC — Department of Defense STTR Phase I: AF18B-T013

Description

Adiabatic reversible logic provides a way to dramatically reduce power dissipation by recovering the energy used to encode information, rather than dissipating the energy to heat, as is done in conventional CMOS. For Phase I we will design test circuits that will evaluate the energy savings in adiabatic reversible logic, as compared to conventional logic. In addition to these smaller circuits, a MIPS-based microprocessor will be designed based on split-rail charge-recovery logic. A challenge in the design of adiabatic circuits is that there are no commercially available design tools to support the design. This is a significant disadvantage relative to conventional designs, where suites of robust tools are available. A set of design tools were previously developed, at the University of Notre Dame, that specifically address the needs of adiabatic circuits, and these tools can be leveraged to aid in the design of the proposed circuits. The project will also evaluate 28 and 90 nm node fabrication technologies, offered through MOSIS, to determine which is best for adiabatic circuits. To compare the dissipation in both reversible and irreversible circuits, diodes and silicon thermocouples will be included in the circuits so that direct measurements of the dissipation can be made.