Torch Technologies, Inc. — Department of Defense STTR Phase II: A14A-T002
Torch Technologies, Inc. — STTR Phase II award from Department of Defense.
Phase II STTR prototype / development signal
- Phase II is where Department of Defense funds deeper R&D after feasibility. Incumbents with Phase II history are serious competitors on adjacent topics.
- Use this award as past-performance context and to map customer organizations for STRATFI/TACFI-style transition planning.
- Obligated amount $572,566 is consistent with substantial Phase II-scale effort; compare to related awards from the same agency.
- Topic code A14A-T002 links this award to a solicitation family — search the same topic stem for incumbents and recompete timing.
- Amount
- $572,566
- Agency
- Department of Defense · Army
- Program / Phase
- STTR · Phase II
- Topic
- A14A-T002
- Solicitation
- 2014.0
- NAICS
- —
- Place of performance
- AL
- Period
- 2015-12-17 → 2017-12-17
Description
Random numbers are essential for a growing number of modern applications. As computer speed and communications bandwidth have increased the potential for practical streaming cipher and large-scale Monte Carlo simulations have become technologically feasible. For these and other applications, ultrafast random number generators are essential. This is intuitively clear. Additionally, however, the ideality of true random numbers must also be imposed for the sake of key security and stochastic distribution fidelity. Pseudorandom numbers are insufficient. Interestingly, these stringent specifications can be met through the deterministic phenomenon of dynamical chaos. Chaotic physical systems, based on the concept of exactly-solvable chaos, naturally produce symbol sequences that are provably stochastically ideal. Thus far, in a Phase I STTR, we have demonstrated, at a proof-of-principle level, that the concept is soundly based and that suitable electronic circuits for the application are realizable. In this Phase II proposal, we present a plan to mature the true random number generator in terms of stochastic fidelity, data and entropy rates, performance stability, environmental robustness and reproducibility, culminating in an Application Specific Integrated Circuit (ASIC) that will be subjected to standard tests for randomness and other design specifications. Test results, operational theory and user data will be documented.