SILICON ASSURANCE LLC — National Science Foundation STTR Phase II: S

Description

The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase II project is to address hardware security and trust issues that are threatening the semiconductor supply chain. Various threats exist from the design stage till the end of the life of chips, such as malicious logic insertion, intellectual property (IP) theft, reverse engineering, backdoor insertion, and information leakage from fabricated chips. Ensuring the security of the supply chain necessitates enhancing chip integrity through proactive measures starting from the design stage to distribution. With security concerns increasingly gaining prominence in specific market segments, such as automotive, defense, and healthcare, various stakeholders, such as device manufacturers, system integrators, end users, and governments are voicing the need for a trusted semiconductor supply chain. Using the proposed software platform, stakeholders of the chip industry will be able to address security challenges at a low cost, without needing trained experts. Furthermore, the team's tools will contribute to minimizing electronic waste generated from refabricating flawed chips and developing software patches that reduce the performance of insecure systems. The proposed technologies will drive chip designers to prioritize enhancing chip security, ensuring competitiveness in environments where secure systems are essential._x000D_ _x000D_ This Small Business Innovation Research (SBIR) Phase II project seeks to address the challenge of commercial deployment of hardware security softwareto detect, assess, and mitigate hardware security vulnerabilities in system-on-chip (SoC) designs. By utilizing a novel methodology, the tool converts Common Weakness Enumerations (CWEs) into a formal description of security properties, which the platform's remaining tools can interpret to identify commonly occurring errors and vulnerabilities in hardware designs. The software seamlessly integrates with major commercial electronic design automation (EDA) tool flow, enhancing the deployment of hardware security software. The toolsets detect security issues in SoCs, including access control violations, asset leakage, and malicious logic or backdoors. The software considers security concerns in the global electronic supply chain involving untrusted entities. The team will collaborate with industry leaders to ensure widespread accessibility. Partnerships with several design companies will demonstrate the unique capabilities of the tool to analyze large designs, e.g., RISC-V processors, and detect a wide array of security vulnerabilities. The utilization of the product will significantly enhance the technology readiness level (TRL) and drive widespread adoption._x000D_ _x000D_ This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.