GRAF RESEARCH CORPORATION — Department of Defense SBIR Phase I: DTRA224-003

Description

The Phase I effort of this program builds on our experience in developing automated fault-injection and testing frameworks. We will expand upon the CPU-based fault injection methodology developed as part of the Dynamic Robust Single Event Upset Simulator (DrSEUs) to also target FPGA resources. This updated methodology will serve as the foundation for an automated fault injection platform that targets complex System-on-Chip (SoC) devices that support heterogeneous applications executing across both CPU and FPGA resources and can be further expanded to support additional resources in future phases. We have been developing a generalized framework for automated testing and analysis of microelectronics on independent funding. This platform already includes support for many of the interfaces that will be required to implement the fault injection and execution monitoring capabilities of the updated methodology. Therefore, we will also be investigating the integration of the updated fault-injection methodology into the Benches platform in this program. The result of the first phase will be a feasibility analysis using the Xilinx Versal SoC as a proof-of-concept device and will include a plan for full prototype development in the second phase.